1. Field of the Invention
This invention relates to an open high-speed bus for microcomputer systems, and especially to an open high-speed local system bus which is decoupled from the I/O and provides a consistent interface to the CPU subsystem, memory subsystem, graphics subsystem and peripheral subsystem.
2. Description of the Prior Art
I/O (input/output) bottlenecks are typically present in current PC (personal computer) architectures. In the IBM PC AT/MCA or industry standard EISA architecture, the CPU (central processing unit) is closely coupled with I/O peripherals. That coupling occurs through the I/O bus, which is simply a buffered CPU local bus. With this tightly coupled architecture, any bus activity by peripherals on the I/O bus will affect the CPU and system memory performance. As CPU speed increases, the I/O performance penalty is multiplied.
Intel's 386/486 microprocessors place even greater demands on the traditional PC AT/MCA architecture. While the traditional highly integrated chip set approach offers cost benefits, it cannot overcome the inherent performance limitations of the PC AT/MCA architecture.